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ltc2302/ltc2306 1 23026fa typical application features applications description low noise, 500ksps, 1-/2-channel, 12-bit adcs the ltc ? 2302/ltc2306 are low noise, 500ksps, 1-/2-chan- nel, 12-bit adcs with an spi/microwire compatible serial interface. these adcs include a fully differential sample-and-hold circuit to reduce common mode noise. the internal conversion clock allows the external serial output data clock (sck) to operate at any frequency up to 40mhz. the ltc2302/ltc2306 operate from a single 5v supply and draw just 2.8ma at a sample rate of 500ksps. the auto-shutdown feature reduces the supply current to 14a at a sample rate of 1ksps. the ltc2302/ltc2306 are packaged in a tiny 10-pin 3mm 3mm dfn. the low power consumption and small size make the ltc2302/ltc2306 ideal for battery-operated and portable applications, while the 4-wire spi compat- ible serial interface makes these adcs a good match for isolated or remote data acquisition systems. 8192 point fft, f in = 1khz (ltc2306) n 12-bit resolution n 500ksps sampling rate n low noise: sinad = 72.8db n guaranteed no missing codes n single 5v supply n auto-shutdown scales supply current with sample rate n low power: 14mw at 500ksps 70w at 1ksps 35w sleep mode n 1-channel (ltc2302) and 2-channel (ltc2306) versions n unipolar or bipolar input ranges (software selectable) n internal conversion clock n spi/microwire ? compatible serial interface n separate output supply ov dd (2.7v to 5.25v) n software compatible with the ltc2308 n 10-pin (3mm 3mm) dfn package n high speed data acquisition n industrial process control n motor control n accelerometer measurements n battery-operated instruments n isolated and/or remote data acquisition type number of input channels 128 int reference ltc2308 ext reference ltc2302 ltc2306 l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. sdi sdo sck convst 23026 ta01 serial port analog input mux ch0 (in + ) ch1 (in C ) analog inputs 0v to 4.096v unipolar 2.048v bipolar v ref 2.7v to 5.25v serial data link to asic, pld, mpu, dsp or shift register ltc2302 ltc2306 v dd ov dd gnd 0.1 f 5v 12-bit 500ksps adc + C 0.1 f pin names in parenthesis refer to ltc2302 10 f 0.1 f 10 f frequency (khz) 0 C40 C20 0 200 23026 ta01b C60 C80 50 100 150 250 C100 C120 C50 C30 C10 C70 C90 C110 C130 C140 magnitude (db) f smpl = 500khz sinad = 72.8db thd = C88.7db
ltc2302/ltc2306 2 23026fa absolute maximum ratings supply voltage (v dd , ov dd ) ......................... ? 0.3v to 6v analog input voltage (note 3) ch0(in + )-ch1(in ? ), ref ..............................(gnd ? 0.3v) to (v dd + 0.3v) digital input voltage (note 3) .............................(gnd ? 0.3v) to (v dd + 0.3v) (notes 1, 2) lead free finish tape and reel part marking* package description temperature range ltc2302cdd#pbf ltc2302cdd#trpbf ldgv 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2302idd#pbf ltc2302idd#trpbf ldgv 10-lead (3mm 3mm) plastic dfn ? 40c to 85c ltc2306cdd#pbf ltc2306cdd#trpbf ldgw 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2306idd#pbf ltc2306idd#trpbf ldgw 10-lead (3mm 3mm) plastic dfn ? 40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ order information top view 11 ltc2302 dd package 10-lead (3mm s 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 ov dd sck sdi gnd v ref sdo convst v dd in + in ? t jmax = 150c, s 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 ov dd sck sdi gnd v ref sdo convst v dd ch0 ch1 t jmax = 150c,
ltc2302/ltc2306 3 23026fa converter and multiplexer characteristics symbol parameter conditions min typ max units v in + absolute input range (ch0, ch1, in + ) (note 9) l C0.05 refcomp v v in C absolute input range (ch0, ch1, in C ) unipolar (note 9) bipolar (note 9) l l C0.05 C0.05 0.25 ? refcomp 0.75 ? refcomp v v v in + C v in C input differential voltage range v in = v in + C v in C (unipolar) v in = v in + C v in C (bipolar) l l 0 to v ref v ref /2 v v i in analog input leakage current l 1 a c in analog input capacitance sample mode hold mode 55 5 pf pf cmrr input common mode rejection ratio 70 db the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 4, 5) parameter conditions min typ max units resolution (no missing codes) l 12 bits integral linearity error (note 6) l 0.3 1 lsb differential linearity error l 0.25 1 lsb bipolar zero error (note 7) l 1 6 lsb bipolar zero error drift 0.002 lsb/c unipolar zero error (note 7) l 1 6 lsb unipolar zero error drift 0.002 lsb/c unipolar zero error match (ltc2306) 0.3 3 lsb bipolar full-scale error (note 8) l 1.5 8 lsb bipolar full-scale error drift 0.05 lsb/c unipolar full-scale error (note 8) l 1.2 6 lsb unipolar full-scale error drift 0.05 lsb/c unipolar full-scale error match (ltc2306) 0.3 3 lsb analog input the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v ref input range l 0.1 v dd v i ref reference input current f smpl = 0ksps, v ref = 4.096v f smpl = 500ksps, v ref = 4.096v l l 50 230 80 260 a a c ref reference input capacitance 55 pf reference input the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4)
ltc2302/ltc2306 4 23026fa symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in high level input current v in = v dd l 10 a c in digital input capacitance 5pf v oh high level output voltage ov dd = 4.75v, i out = C10a ov dd = 4.75v, i out = C200a l 4 4.74 v v v ol low level output voltage ov dd = 4.75v, i out = 160a ov dd = 4.75v, i out = 1.6ma l 0.05 0.4 v v i oz hi-z output leakage v out = 0v to ov dd , convst high l 10 a c oz hi-z output capacitance convst high 15 pf i source output source current v out = 0v C10 ma i sink output sink current v out = ov dd 10 ma digital inputs and digital outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v dd supply voltage l 4.75 5 5.25 v ov dd output driver supply voltage l 2.7 5.25 v i dd supply current sleep mode c l = 25pf convst = 5v, conversion done l l 2.8 7 3.5 15 ma a p d power dissipation sleep mode 14 35 mw w power requirements the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 1khz l 71 72.8 db snr signal-to-noise ratio f in = 1khz l 71 73.2 db thd total harmonic distortion f in = 1khz, first 5 harmonics l C88 C78 db sfdr spurious free dynamic range f in = 1khz l 79 89 db channel-to-channel isolation f in = 1khz C109 db full linear bandwidth (note 11) 700 khz C3db input linear bandwidth 25 mhz aperture delay 13 ns transient response full-scale step 240 ns dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (notes 4, 10)
ltc2302/ltc2306 5 23026fa timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units f smpl(max) maximum sampling frequency l 500 khz f sck shift clock frequency l 40 mhz t whconv convst high time (note 9) l 20 ns t hd hold time sdi after sck b l 2.5 ns t sudi setup time sdi stable before sck b l 0ns t whclk sck high time f sck = f sck(max) l 10 ns t wlclk sck low time f sck = f sck(max) l 10 ns t wlconvst convst low time during data transfer (note 9) l 410 ns t hconvst hold time convst low after last sck (note 9) l 20 ns t conv conversion time l 1.3 1.6 s t acq acquisition time 7th sck b to convst b (note 9) l 240 ns t ddo sdo data valid after sck c l = 25pf (note 9) l 10.8 12.5 ns t hdo sdo hold time sck c l = 25pf l 4ns t en sdo valid after convst c l = 25pf l 11 15 ns t dis bus relinquish time c l = 25pf l 11 15 ns t r sdo rise time c l = 25pf 4 ns t f sdo fall time c l = 25pf 4 ns t cyc total cycle time 2s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with v dd and ov dd wired together (unless otherwise noted). note 3: when these pin voltages are taken below ground or above v dd , they will be clamped by internal diodes. these products can handle input currents greater than 100ma below ground or above v dd without latchup. note 4: v dd = 5v, ov dd = 5v, v ref = 4.096v, f smpl = 500ksps, unless otherwise speci? ed. note 5: linearity, offset and full-scale speci? cations apply for a single- ended analog input with respect to gnd for the ltc2306 and in + with respect to in C tied to gnd for the ltc2302. note 6: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: bipolar zero error is the offset voltage measured from C 0.5lsb when the output code ? ickers between 0000 0000 0000 and 1111 1111 1111. unipolar zero error is the offset voltage measured from +0.5lsb when the output code ? ickers between 0000 0000 0000 and 0000 0000 0001. note 8: full-scale bipolar error is the worst-case of C fs or +fs untrimmed deviation from ideal ? rst and last code transitions and includes the effect of offset error. unipolar full-scale error is the deviation of the last code transition from ideal and includes the effect of offset error. note 9: guaranteed by design, not subject to test. note 10: all speci? cations in db are referred to a full-scale 2.048v input with a 4.096v reference voltage. note 11: full linear bandwidth is de? ned as the full-scale input frequency at which the sinad degrades to 60db or 10 bits of accuracy.
ltc2302/ltc2306 6 23026fa typical performance characteristics integral nonlinearity vs output code differential nonlinearity vs output code 1khz sine wave 8192 point fft plot snr vs input frequency sinad vs input frequency thd vs input frequency supply current vs sampling frequency supply current vs temperature (ltc2302) t a = 25c, v dd = ov dd = 5v, v ref = 4.096v, f smpl = 500ksps, unless otherwise noted. output code 0 inl (lsb) 0 0.25 0.50 4096 23026 g01 C0.25 C0.50 C1.00 1024 2048 3072 C0.75 1.00 0.75 output code 0 dnl (lsb) 0 0.25 0.50 4096 23026 g02 C0.25 C0.50 C1.00 1024 2048 3072 C0.75 1.00 0.75 frequency (khz) 0 C40 C20 0 200 23026 g03 C60 C80 50 100 150 250 C100 C120 C50 C30 C10 C70 C90 C110 C130 C140 magnitude (db) snr = 73.2db sinad = 72.8db thd = C89.5db frequency (khz) 1 50 snr (db) 70 75 80 10 100 1000 23026 g04 65 60 55 frequency (khz) 1 50 sinad (db) 70 75 80 10 100 1000 23026 g05 65 60 55 frequency (khz) 1 C80 thd (db) C70 C60 10 100 1000 23026 g06 C90 C85 C75 C65 C95 C100 sampling frequency (ksps) 1 2.0 supply current (ma) 2.5 3.0 3.5 10 100 1000 23026 g07 1.5 1.0 0.5 0 temperature (c) C50 2.0 supply current (ma) 2.2 2.6 2.8 3.0 4.0 3.4 0 50 75 23026 g08 2.4 3.6 3.8 3.2 C25 25 100 125
ltc2302/ltc2306 7 23026fa sleep current vs temperature typical performance characteristics analog input leakage current vs temperature offset error vs temperature full-scale error vs temperature (ltc2302) t a = 25c, v dd = ov dd = 5v, v ref = 4.096v, f smpl = 500ksps, unless otherwise noted. temperature (c) C50 0 sleep current (a) 1 3 4 5 10 7 0 50 75 23026 g09 2 8 9 6 C25 25 100 125 temperature (c) C50 0 input leakage current (na) 100 300 400 500 1000 700 0 50 75 23026 g10 200 800 900 600 C25 25 100 125 temperature (c) C50 C1.0 C1.5 C2.0 C2.5 offset error (lsb) C0.5 0.5 1.0 1.5 2.5 0 50 75 23026 g11 0 2.0 C25 25 100 125 bipolar unipolar temperature (c) C50 full-scale error (lsb) 1.5 25 23026 g12 0 C1.0 C25 0 50 C1.5 C2.0 2.0 1.0 0.5 C0.5 75 100 125 bipolar unipolar
ltc2302/ltc2306 8 23026fa typical performance characteristics integral nonlinearity vs output code differential nonlinearity vs output code 1khz sine wave 8192 point fft plot snr vs input frequency sinad vs input frequency thd vs input frequency supply current vs sampling frequency supply current vs temperature (ltc2306) t a = 25c, v dd = ov dd = 5v, v ref = 4.096v, f smpl = 500ksps, unless otherwise noted. output code 0 inl (lsb) 0 0.25 0.50 4096 23026 g13 C0.25 C0.50 C1.00 1024 2048 3072 C0.75 1.00 0.75 output code 0 dnl (lsb) 0 0.25 0.50 4096 23026 g14 C0.25 C0.50 C1.00 1024 2048 3072 C0.75 1.00 0.75 frequency (khz) 0 C40 C20 0 200 23026 g15 C60 C80 50 100 150 250 C100 C120 C50 C30 C10 C70 C90 C110 C130 C140 magnitude (db) snr = 73.2db sinad = 72.8db thd = C88.7db frequency (khz) 1 50 snr (db) 70 75 80 10 100 1000 23026 g16 65 60 55 frequency (khz) 1 50 sinad (db) 70 75 80 10 100 1000 23026 g17 65 60 55 frequency (khz) 1 C80 thd (db) C70 C60 10 100 1000 23026 g18 C90 C85 C75 C65 C95 C100 sampling frequency (ksps) 1 2.0 supply current (ma) 2.5 3.0 3.5 10 100 1000 23026 g19 1.5 1.0 0.5 0 temperature (c) C50 2.0 supply current (ma) 2.2 2.6 2.8 3.0 4.0 3.4 0 50 75 23026 g20 2.4 3.6 3.8 3.2 C25 25 100 125
ltc2302/ltc2306 9 23026fa sleep current vs temperature typical performance characteristics analog input leakage current vs temperature offset error vs temperature full-scale error vs temperature (ltc2306) t a = 25c, v dd = ov dd = 5v, v ref = 4.096v, f smpl = 500ksps, unless otherwise noted. temperature (c) C50 0 sleep current (a) 1 3 4 5 10 7 0 50 75 23026 g21 2 8 9 6 C25 25 100 125 temperature (c) C50 0 input leakage current (na) 100 300 400 500 1000 700 0 50 75 23026 g22 200 800 900 600 C25 25 100 125 temperature (c) C50 offset error (lsb) 1.5 25 23026 g23 0 C1.0 C25 0 50 C1.5 C2.0 2.0 1.0 0.5 C0.5 75 100 125 bipolar unipolar temperature (c) C50 full-scale error (lsb) 1.5 25 23026 g24 0 C1.0 C25 0 50 C1.5 C2.0 2.0 1.0 0.5 C0.5 75 100 125 bipolar unipolar
ltc2302/ltc2306 10 23026fa pin functions ltc2302 sdo (pin 1): three-state serial data out. sdo outputs the data from the previous conversion. sdo is shifted out serially on the falling edge of each sck pulse. sdo is enabled by a low level on convst. convst (pin 2): conversion start. a rising edge at convst begins a conversion. for best performance, ensure that convst returns low within 40ns after the conversion starts or after the conversion ends. v dd (pin 3): 5v supply. the range of v dd is 4.75v to 5.25v. bypass v dd to gnd with a 0.1f ceramic capacitor and a 10f tantalum capacitor in parallel. in + , in C (pin 4, pin 5): positive (in + ) and negative (in C ) differential analog inputs. v ref (pin 6): reference input. connect an external reference at v ref . the range of the external reference is 0.1v to v dd . bypass to gnd with a minimum 10f tantalum capacitor in parallel with a 0.1f ceramic capacitor. gnd (pin 7): ground. all gnd pins must be connected to a solid ground plane. sdi (pin 8): serial data input. the sdi serial bit stream con? gures the adc and is latched on the rising edge of the ? rst 6 sck pulses. sck (pin 9): serial data clock. sck synchronizes the serial data transfer. the serial data input at sdi is latched on the rising edge of sck. the serial data output at sdo transitions on the falling edge of sck. ov dd (pin 10): output driver supply. bypass ov dd to gnd with a 0.1f ceramic capacitor close to the pin. the range of ov dd is 2.7v to 5.25v. exposed pad (pin 11): exposed pad ground. must be soldered directly to ground plane. ltc2306 sdo (pin 1): three-state serial data out. sdo outputs the data from the previous conversion. sdo is shifted out serially on the falling edge of each sck pulse. sdo is enabled by a low level on convst. convst (pin 2): conversion start. a rising edge at convst begins a conversion. for best performance, ensure that convst returns low within 40ns after the conversion starts or after the conversion ends . v dd (pin 3): 5v supply. the range of v dd is 4.75v to 5.25v. bypass v dd to gnd with a 0.1f ceramic capacitor and a 10f tantalum capacitor in parallel. ch0, ch1 (pin 4, pin 5): channel 0 and channel 1 analog inputs. ch0, ch1 can be con? gured as single-ended or differential input channels. see the analog input multi- plexer section. v ref (pin 6): reference input. connect an external reference at v ref .the range of the external reference is 0.1v to v dd . bypass to gnd with a minimum 10f tantalum capacitor in parallel with a 0.1f ceramic capacitor. gnd (pin 7): ground. all gnd pins must be connected to a solid ground plane. sdi (pin 8): serial data input. the sdi serial bit stream con? gures the adc and is latched on the rising edge of the ? rst 6 sck pulses. sck (pin 9): serial data clock. sck synchronizes the serial data transfer. the serial data input at sdi is latched on the rising edge of sck. the serial data output at sdo transitions on the falling edge of sck. ov dd (pin 10): output driver supply. bypass ov dd to ognd with a 0.1f ceramic capacitor close to the pin. the range of ov dd is 2.7v to 5.5v. exposed pad (pin 11): exposed pad ground. must be soldered directly to ground plane.
ltc2302/ltc2306 11 23026fa block diagram test circuits timing diagrams voltage waveforms for sdo delay times, t ddo and t hdo voltage waveforms for t dis load circuit for t dis waveform 1 load circuit for t dis waveform 2, t en sdi sdo sck convst 23026 bd serial port analog input mux ch0 (in + ) ch1 (in C ) v ref ltc2302 ltc2306 pin names in parenthesis refer to ltc2302 v dd ov dd gnd 12-bit 500ksps adc + C sdo test point v dd 3k c l 23026 tc01 sdo test point 3k c l 23026 tc02 sck sdo v il t ddo t hdo v oh v ol 23026 td01 sdo waveform 1 (see note 1) v ih t dis 90% 10% sdo waveform 2 (see note 2) convst note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control 23026 td02
ltc2302/ltc2306 12 23026fa timing diagrams t wlclk (sck low time) t whclk (sck high time) t hd (hold time sdi after sck b ) t sudi (setup time sdi stable before sck b ) voltage waveforms for t en voltage waveforms for sdo rise and fall times t r , t f applications information 23026 td03 sck sdi t wlclk t whclk t hd t sudi 23026 td04 convst sdo t en sdo t r t f 23004 td05 v oh v ol overview the ltc2302/ltc2306 are low noise, 500ksps, 1-/2- channel, 12-bit successive approximation register (sar) a/d converters. the ltc2306 includes a 2-channel analog input multiplexer (mux) while the ltc2302 includes an input mux that allows the polarity of the differential input to be selected. both adcs include an spi-compatible serial port for easy data transfers and can operate in either unipolar or bipolar mode. unipolar mode should be used for single-ended operation with the ltc2306, since single-ended input signals are always referenced to gnd. the ltc2302/ltc2306 can be put into a power-down sleep mode during idle periods to save power. conversions are initiated by a rising edge on the convst input. once a conversion cycle has begun, it cannot be restarted. between conversions, a 6-bit input word (d in ) at the sdi input con? gures the mux and programs vari- ous modes of operation. as the d in bits are shifted in, data from the previous conversion is shifted out on sdo. after the 6 bits of the d in word have been shifted in, the adc begins acquiring the analog input in preparation for the next conversion as the rest of the data is shifted out. the acquire phase requires a minimum time of 240ns for the sample-and-hold capacitors to acquire the analog input signal. during the conversion, the internal 12-bit capacitive charge-redistribution dac output is sequenced through a successive approximation algorithm by the sar starting from the most signi? cant bit (msb) to the least signi? cant bit (lsb). the sampled input is successively compared with binary weighted charges supplied by the capacitive dac using a differential comparator. at the end of a conversion, the dac output balances the analog input. the sar contents (a 12-bit data word) that represent the sampled analog input are loaded into 12 output latches that allow the data to be shifted out. programming the ltc2306 and ltc2302 the software compatible ltc2302/ltc2306/ltc2308 fam- ily features a 6-bit d in word to program various modes of operation. dont care bits (x) are ignored. the sdi data bits are loaded on the rising edge of sck, with the s/d bit loaded on the ? rst rising edge (see figure 6 in the timing
ltc2302/ltc2306 13 23026fa applications information figure 1a. example mux con? gurations figure 1b. changing the mux assignment on the fly and control section). the input data word for the ltc2306 is de? ned as follows: s/d o/s x x uni x s/d = single-ended/ differential bit o/s = odd/ sign bit uni = unipolar/ bipolar bit x = don t care for the ltc2302, the input data word is de? ned as: x o/s x x uni x analog input multiplexer the analog input mux is programmed by the s/d and o/s bits of the d in word for the ltc2306 and the o/s bit of the d in word for the ltc2302. table 1 and table 2 list mux con? gurations for all combinations of the con? guration bits. figure 1a shows several possible mux con? gurations and figure 1b shows how the mux can be recon? gured from one conversion to the next. driving the analog inputs the analog inputs of the ltc2302/ltc2306 are easy to drive. each of the analog inputs of the ltc2306 (ch0 and ch1) can be used as a single-ended input relative to gnd or as a differential pair. the analog inputs of the ltc2302 (in + , in C ) are always con? gured as a differential pair. regardless of the mux con? guration, the + and C inputs are sampled at the same instant. any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the sample-and-hold cir- cuit. the inputs draw only one small current spike while ch0 ch1 (C) gnd 2 single-ended + 1 differential + ( C ) + ltc2306 ltc2306 23026 f01a C ( + ) { ch0 ch1 1 differential + ( C ) ltc2302 C ( + ) { in + in C ch0 ch1 (C) gnd ltc2306 2nd conversion + 1st conversion + + 23026 f01b C { ch0 ch1 ltc2306 s/d 0 0 1 1 o/s 0 1 0 1 ch0 + C + ch1 C + + with respect to gnd note: unipolar mode should be used for single-ended operation, since input signals are always referenced to gnd table 1. channel con?guration for the ltc2306 o/s 0 1 in + + C in C C + table 2. channel con?guration for the ltc2302
ltc2302/ltc2306 14 23026fa applications information figure 2b. analog input equivalent circuit for large filter capacitances figure 2a. analog input equivalent circuit charging the sample-and-hold capacitors during the acquire mode. in conversion mode, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low, the adc inputs can be driven directly. otherwise, more acquisition time should be allowed for a source with higher impedance. reference a low noise, stable reference is required to ensure full performance. the lt ? 1790 and lt6660 are adequate for most applications. the lt6660 is available in 2.5v, 3v, 3.3v and 5v versions, and the lt1790 is available in 1.25v, 2.048v, 2.5v, 3v, 3.3v, 4.096v and 5v versions. the exceptionally low input noise allows the input range to be optimized for the application by changing the reference voltage. the v ref input must be decoupled with a 10f capacitor in parallel with a 0.1f capacitor, so verify that the device providing the reference voltage is stable with capacitive loads. if the voltage reference is 5v and can supply 5ma, it can be used for both v ref and v dd . v dd must be connected to a clean analog supply, and a quiet 5v reference voltage makes a convenient supply for this purpose. input filtering the noise and distortion of the input ampli? er and other circuitry must be considered since they will add to the adc noise and distortion. therefore, noisy input circuitry should be ? ltered prior to the analog inputs to minimize noise. a simple 1-pole rc ? lter is suf? cient for many applications. the analog inputs of the ltc2302/ltc2306 can be modeled as a 55pf capacitor (c in ) in series with a 100 1 resistor (r on ) as shown in figure 2a. c in gets switched to the selected input once during each conversion. large ? lter rc time constants will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle to 12-bit resolution within the acquisition time (t acq ) if dc accuracy is important. when using a ? lter with a large c filter value (e.g., 1f), the inputs do not completely settle and the capacitive input switching currents are averaged into a net dc current (i dc ). in this case, the analog input can be modeled by an equivalent resistance (r eq = 1/(f smpl ? c in )) in series with an ideal voltage source (v ref /2) as shown in figure 2b. the magnitude of the dc current is then approximately i dc = (v in C v ref /2)/r eq , which is roughly proportional to v in . to prevent large dc drops across the resistor r filter , a ? lter with a small resistor and large capacitor should be chosen. when running at the minimum cycle time of 2s, the input current equals 106a at v in = 5v, which amounts to a full-scale error of 0.5lsb when using a ? lter resistor (r filter ) of 4.7 1 . applications requiring lower sample rates can tolerate a larger ? lter resistor for the same amount of full-scale error. c in 55pf r on 100 r source v in ltc2302 ltc2306 input (ch0, ch1 in + , in C ) c1 23026 f02a r eq 1/(f smpl ? c in ) v ref /2 r filter i dc v in ltc2302 ltc2306 input (ch0, ch1 in + , in C ) c filter 23026 f02b + C
ltc2302/ltc2306 15 23026fa applications information figure 3a. optional rc input filtering for single-ended input figure 3b. optional rc input filtering for differential inputs figure 4. 1khz sine wave 8192 point fft plot (ltc2306) figures 3a and 3b show respective examples of input ? ltering for single-ended and differential inputs. for the single-ended case in figure 3a, a 50 1 source resistor and a 2000pf capacitor to ground on the input will limit the input bandwidth to 1.6mhz. high quality capacitors and resistors should be used in the rc ? lter since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal ? lm surface mount resistors are much less susceptible to both problems. dynamic performance fft (fast fourier transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequencies outside the fundamental. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band-limited to frequencies from above dc and below half the sampling frequency. figure 4 shows a typical sinad of 72.8db with a 500khz sampling rate and a 1khz input. a snr of 73.2db can be achieved with the ltc2302/ltc2306. 23026 f03a ch0, ch1 ltc2306 v ref 2000pf 10f 0.1f 0.1f 50 analog input lt1790a-4.096 v out v in 5v 1000pf 23026 f03b ch0, in + ch1, in C ltc2302 ltc2306 v ref 1000pf 1000pf 10f 0.1f 50 50 differential analog inputs 0.1f lt1790a-4.096 v out v in 5v total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency(f smpl /2). thd is expressed as: thd vvv v v n = ++ + 20 2 2 3 2 4 22 1 log ... where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. frequency (khz) 0 C40 C20 0 200 23026 f04 C60 C80 50 100 150 250 C100 C120 C50 C30 C10 C70 C90 C110 C130 C140 magnitude (db) snr = 73.2db sinad = 72.8db thd = C88.7db
ltc2302/ltc2306 16 23026fa applications information internal conversion clock the internal conversion clock is factory trimmed to achieve a typical conversion time (t conv ) of 1.3s and a maximum conversion time of 1.6s over the full operating temperature range. with a minimum acquisition time of 240ns, a throughput sampling rate of 500ksps is tested and guaranteed. digital interface the ltc2302/ltc2306 communicate via a standard 4 -wire spi compatible digital interface. the rising edge of convst initiates a conversion. after the conversion is ? nished, pull convst low to enable the serial output (sdo). the adc then shifts out the digital data in 2s complement format when operating in bipolar mode or in straight binary format when in unipolar mode, based on the setting of the uni bit. for best performance, ensure that convst returns low within 40ns after the conversion starts (i.e., before the ? rst bit decision) or after the conversion ends. if convst is low when the conversion ends, the msb bit will appear at sdo at the end of the conversion and the adc will remain powered up. timing and control the start of a conversion is triggered by the rising edge of convst. once initiated, a new conversion cannot be restarted until the current conversion is complete. figures 6 and 7 show the timing diagrams for two different examples of convst pulses. example 1 (figure 6) shows convst staying high after the conversion ends. if convst is high after the t conv period, the ltc2302/ltc2306 enter sleep mode (see sleep mode for more details). when convst returns low, the adc wakes up and the most signi? cant bit (msb) of the output data sequence at sdo becomes valid after the serial data bus is enabled. all other data bits from sdo transition on the falling edge of each sck pulse. con? guration data (d in ) is loaded into the ltc2302/ltc2306 at sdi, starting with the ? rst sck rising edge after convst returns low. the s/d bit is loaded on the ? rst sck rising edge. example 2 (figure 7) shows convst returning low be- fore the conversion ends. in this mode, the adc and all internal circuitry remain powered up. when the conver- sion is complete, the msb of the output data sequence at sdo becomes valid after the data bus is enabled. at this point(t conv 1.3s after the rising edge of convst), pulsing sck will shift data out at sdo and load con? gura- tion data (d in ) into the ltc2302/ltc2306 at sdi. the ? rst sck rising edge loads the s/d bit. sdo transitions on the falling edge of each sck pulse. figures 8 and 9 are the transfer characteristics for the bipolar and unipolar modes. data is output at sdo in 2s complement format for bipolar readings or in straight binary for unipolar readings. sleep mode the adc enters sleep mode when convst is held high after the conversion is complete (t conv ). the supply cur- rent decreases to 7a in sleep mode between conversions, thereby reducing the average power dissipation as the sample rate decreases. for example, the ltc2302/ltc2306 draw an average of 14a with a 1ksps sampling rate. the ltc2302/ltc2306 power down all circuitry when in sleep mode. board layout and bypassing to obtain the best performance, a printed circuit board with a solid ground plane is required. layout for the printed circuit board should ensure digital and analog signal lines are separated as much as possible. care should be taken not to run any digital signal alongside an analog signal. all analog inputs should be shielded by gnd. v ref and v dd should be bypassed to the ground plane as close to the pin as possible. maintaining a low impedance path for the common return of these bypass capacitors is essential to the low noise operation of the adc. these traces should be as wide as possible. see figure 5 for a suggested layout.
ltc2302/ltc2306 17 23026fa applications information figure 5. suggested layout figure 6. ltc2302/ltc2306 timing with a long convst pulse uni o/s s/d b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 t conv convst sck sdi sdo hi-z hi-z 23026 f06 msb lsb t acq t wlconvst t cyc 123456789101112 s/d bit is a dont care (x) for the ltc2302 sleep v dd , bypass 0.1f||10f, 0603 input filter capacitors ov dd , bypass 0.1f, 0603 23026 f05 v ref , bypass 0.1f||10f 0603 solid ground plane
ltc2302/ltc2306 18 23026fa applications information figure 7. ltc2302/ltc2306 timing with a short convst pulse s/d bit is a dont care (x) for the ltc2302 uni o/s s/d b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 t conv convst sck sdi sdo hi-z hi-z 23026 f07 msb lsb t acq t hconvst t cyc 1 2 3 4 5 6 7 8 9 10 11 12 t whconv figure 8. ltc2302/ltc2306 bipolar transfer characteristics (2s complement) figure 9. ltc2302/ltc2306 unipolar transfer characteristics (straight binary) input voltage (v) 0v output code (twos complement) C1 lsb 23026 f08 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 C 1lsb Cfs/2 fs = 4.096v 1lsb = fs/2 n 1lsb = 1mv input voltage (v) output code 20026 f09 111...111 111...110 100...001 100...000 000...000 000...001 011...110 011...111 fs C 1lsb 0v unipolar zero fs = 4.096v 1lsb = fs/2 n 1lsb = 1mv
ltc2302/ltc2306 19 23026fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc
ltc2302/ltc2306 20 23026fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0908 rev a ? printed in usa typical application clock squaring/level shifting circuit allows testing with rf sine generator, convert re-timing flip-flop preserves low jitter clock timing sdi sdo sck convst serial port analog input mux ch0 (in + ) ch1 (in C ) v ref convert enable master clock rf signal generator or other low jitter source v cc 0.1f nc7svu04p5x ltc2302 ltc2306 v dd ov dd gnd master clock convert enable jitter 0.1f 12-bit 500ksps adc + C 10f 0.1f 1k 10f 0.1f qd pre v cc nl17sz74 control logic (fpga, cpld, dsp , etc.) q clr 1k 23026 ta02 50 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? convst data transfer related parts part number description comments ltc1417 14-bit, 400ksps serial adc 20mw, unipolar or bipolar, internal reference, ssop-16 package ltc1468/lt1469 single/dual 90mhz, 22v/s, 16-bit accurate op amps low input offset: 75v/125v ltc1609 16-bit, 200ksps serial adc 65mw, con? gurable bipolar and unipolar input ranges, 5v supply ltc1790 micropower low dropout reference 60a supply current, 10ppm/c, sot-23 package ltc1850/ltc1851 10-bit/12-bit, 8-channel, 1.25msps adcs parallel output, programmable mux and sequencer, 5v supply ltc1852/ltc1853 10-bit/12-bit, 8-channel, 400ksps adcs parallel output, programmable mux and sequencer, 3v or 5v supply ltc1860/ltc1861 12-bit, 1-/2-channel 250ksps adcs in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1860l/ltc1861l 3v, 12-bit, 1-/2-channel 150ksps adcs 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc1863/ltc1867 12-/16-bit, 8-channel 200ksps adcs 6.5mw, unipolar or bipolar, internal reference, ssop-16 package ltc1863l/ltc1867l 3v, 12-/16-bit, 8-channel 175ksps adcs 2mw, unipolar or bipolar, internal reference, ssop-16 package ltc1864/ltc1865 16-bit, 1-/2-channel 250ksps adcs in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1864l/ltc1865l 3v, 16-bit, 1-/2-channel 150ksps adcs in msop 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc2308 12-bit, 8-channel 500ksps adc 5v, internal reference, 4mm 4mm qfn packages

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